Engineering

ISBT Reasoning for all banking PO,Clerk,IBPS PO,Railway,SSC,IAS,OAS Exams

Q1.	In a basic transmission line, the voltage at the receiving end without load is 660 V; and it is 420 V with full load. What is the percentage of voltage regulation ?

1)	47%	2)	57%
3)	67%	4)	77%
5)	None of these

Q2.	A disk unit has 24 recording surfaces. It has a total of 14000 cylinders. There is an average of 400 sectors per track. Each sector contains 512 bytes of data. What is the data transfer rate at a rotational speed of 7200 r.p.m.?

1)	68.80 ×10^6 bytes/s	2)	24.58 ×10^6 bytes/s
3)	68.80 ×10^3 bytes/s	4)	24.58 ×10^3 bytes/s
5)	None of these

Q3.	Consider the following processes which arrived in the order P1, P2 and P3: Process            Burst Time   P1                    24 ms   P2                     3 ms   P3                     3 ms What is the average waiting time by FCFS scheduling ?

1)	17 ms	2)	19 ms
3)	21 ms	4)	23 ms
5)	None of these

Q4.	Consider the following statements regarding the functions of an operating system in a computer: 1. It controls hardware access 2. It manages files and folders 3. It provides a user interface 4. It manages applications Which of the above statements are correct ?

1)	1, 2 and 3 only	2)	1, 2 and 4 only
3)	3 and 4 only (d)	4)	1, 2, 3 and 4
5)	None of these

Q5.	The noise factor of an attenuator pad that has an insertion loss of 6 dB is -

1)	0.25	2)	0.5
3)	2	4)	4
5)	None of these

Q6.	A weighted complete graph with n vertices has weights 2|i – j| at edges (vj, vj). The weight of a minimum spanning tree is -

1)	n2/2	2)	n/2
3)	2n – 2	4)	n – 1
5)	None of these

Q7.	An asynchronous link between two computers uses the start-stop scheme, with one start bit and one stop bit, and a transmission rate of 48.8 kbits/s. What is the effective transmission rate as seen by the two computers ?

1)	480 bytes/s	2)	488 bytes/s
3)	4800 bytes/s	4)	4880 bytes/s
5)	None of these

Q8.	A cache line has 128 bytes. The main memory has latency 64 ns and bandwidth 1 GB/s. The time required to fetch the entire cache line is -

1)	32 ns	2)	64 ns
3)	96 s	4)	192 ns
5)	None of these

Q9.	A 32 kB RAM is formed by 16 numbers of a particular type of SRAM IC. If each IC needs 14 address bits, what is the IC capacity ?

1)	4 kbits	2)	8 kbits
3)	16 kbits	4)	32 kbits
5)	None of these

Q10.	For derivative control action, the actuating signal consists of proportional error signal with addition of -

1)	derivative of the error signals	2)	integral of the error signals
3)	steady-state error	4)	a constant which is a function of the system type
5)	None of these